Innovation

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Scale Up

Breaking the Copper Limit :
Brillink Redefines Short-Reach Interconnects

Extending on-chip performance to more than 10 meters with chip-scale interconnect density exceeding 10 Tbps/mm².

Unique Feature

As Moore’s Law slows, Brillink redefines I/O interconnects. Our proprietary Micro LED/VCSEL array technology achieves 10 Tbps/mm², matching copper-wire bandwidth density while extending high-performance reach to more than 10 meters. By replacing power-hungry single-lane speeds with 500+ high-density matrix channels, we deliver ultra-low power consumption (<0.5 pJ/bit)—breaking the bottleneck of signal decay and enabling next-generation Scale-Up architectures.

Micro LED OE Engine Function Block

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Technology Breakthrough

NOW

Low Bandwidth Micro LED

Low Channel Count

Huge Loss of Array Fiber Coupling

Low Sensitivity PD & Operation Temperature

BRILLINK

> 4 Gbps Gbps / Lane

> 500 Channel Count

< 1 dB Fiber Coupling Loss

< -25 dBm PD Sensitivity

> 125°C High Temperature Operation

High Sensitivity PD (-25 ~ -30 dBm) Enhancing Energy Efficiency

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Scale Out

The Dimensional Revolution for High-Density AI Clusters

Leveraging proprietary 2D vertical coupler arrays and miniature modulation, we deliver a 400 G/Lane Scale-Out light engine with an 80% smaller footprint.

Future Interconnect

Revolutionizing Interconnects : From Linear to Planar Architecture

Traditional optical interconnects are limited by bulky MZMs or unstable, narrow-band MRMs. Brillink breaks these physical constraints by pioneering 2D Vertical Coupler Arrays and Next-Gen Ultra-Compact Modulators.
Our innovation reduces modulator size to 1/10th of standard MZMs while offering a 5–10x wider operating wavelength range than MRMs, ensuring superior environmental robustness. This architecture shrinks the optical engine by 80%, enabling >200 Gbps / Lane single-lane speeds with pristine signal integrity—delivering the ultimate high-density PIC solution for AI Scale-Out.